1. Field of the Invention
The present invention relates to a carrier substrate, a fabrication method thereof, a printed circuit board using the same, and a fabrication method thereof, and more particularly, to a carrier substrate without a land in a via and a core in the substrate, a fabrication method thereof, a printed circuit board using the same, and a fabrication method thereof.
2. Description of the Related Art
A printed circuit board (PCB) is used to allow the components of an electronic device to be mounted thereon and for wirings. The PCB is configured such that a thin plate made of copper or the like is attached on one surface of a phenol resin insulating plate or an epoxy resin insulating plate and is subsequently etched according to the wiring patterns of circuits (i.e., corroded so as to be removed while leaving circuits in lines) to form required circuits and a hole is formed to allow components to be attached and mounted thereon.
PCBs include a single sided PCB with wirings formed only on one side of an insulating substrate, a double-sided PCB with wirings formed on both sides of an insulating layer, and a multi-layer PCB with wirings formed on multiple layers. In the past, component elements and circuit patterns are simple to fit onto the single side PCB, but recently, as circuits have become increasingly complicated and the demands placed on a circuit having high density have grown, double-sided PCBs or multi-layer PCBs are generally used.
The multi-layer PCB is configured by alternately stacking circuit layers and insulating layers. This structure needs a via to electrically connect the inner circuit layer and the outer circuit layer through the insulating layer. The manufacturing of the multilayer PCB through a build-up process necessarily accompanies a process of forming a via hole in the insulating layer stacked on the inner circuit layer, which can be electrically connected with the outer circuit layer.
In this case, a land is necessarily formed at a portion connected with an upper circuit layer through the via hole for a stable electrical connection between the layers. The land is designed in consideration of a processing error in mechanical processing to form the via, an error of exposing facilities used for forming the upper circuit layer, and deformation of a raw material in use during a process. The deviation in the facilities, materials, and processes is unavoidable, so the designing of a land has been considered natural in order to increase productivity and a processing yield.
However, advancements in the electronic industry have promoted the development of high-integrated semiconductors and accelerated the reduction in size of electronic components, so, in line with this, PCBs on which the electronic components are to be mounted are now required to be smaller, thinner, and more highly integrated. To this end, efforts to make the wirings of PCBs finer, and to reduce the space of the via have continued, but the presence of the land restricts the high integration of PCBs. Also, a matching force of laser facilities for forming the via has been improved to enhance interlayer matching of the highly integrated substrate, and new high-matching exposure facilities have been developed to form fine circuits, but improvements of these facilities require a great deal of time and, basically, these facilities have a limitation in that they cannot completely remove a land.